Each check, what it tests¶
For anyone who clicked a check’s name on an fpgas.online dashboard, or who runs fpgas-verify on an Arty A7, NeTV2, Fomu EVT, TT FPGA demo board or Acorn: a section for every check, named as the dashboards name it, with, for each board type that gets it, what it checks and what the check runs, and the board types it is not for and why. How the whole check runs is on what the check tests on each board and what an Acorn check tests.
Checks: Boot check, Check ran, pcie-link, pcie-bar0, rp1-pio, jtag, flash, ddr, p2-uart, p2-serial, scratch, p2-gpio, wiring, power-cycle, uart, ethernet, header, foboot, foboot-after, sdk, dip-switches, spram.
Boot check¶
The check fpgas-verify runs at every boot of a Pi with an FPGA board: it finds the board, runs every check below that the board’s type gets, in order, and reports one result for the boot: pass (every check passed), fail (a check failed), error (the check could not finish), or missing (it found no board). The dashboards show it as the Boot check column; a board is offered to visitors only after a pass. Reading the result says what each result means, and common failures what to do about each message.
Check ran¶
When the boot check of the boot the Pi is running reported its result (its fpga-verified event). A Pi checks again at its next boot; until then this time does not change.
pcie-link¶
Board |
Variants |
What it checks |
What the check runs |
|---|---|---|---|
Sqrl Acorn |
every |
the PCIe link’s speed and width are the setup’s |
the link speed and width in sysfs, against the setup’s expected figures ( |
When it fails:
It says |
Meaning, and what to do |
|---|---|
|
the Acorn’s PCIe link is not the setup’s ( |
The messages any check can give (a design that would not load, a test that did not finish, a tool or package missing, a planned test that has no boot-check test yet) are in common failures.
pcie-bar0¶
Board |
Variants |
What it checks |
What the check runs |
|---|---|---|---|
Sqrl Acorn |
every |
over PCIe BAR0: the build running, the flash’s identity, the device DNA, the XADC readings |
over BAR0: which build runs (golden is a fault: the operational slot did not boot), the flash’s identity, the device DNA and the XADC temperature and voltages |
When it fails:
It says |
Meaning, and what to do |
|---|---|
|
the Acorn’s operational slot did not boot; it fell back to golden |
The messages any check can give (a design that would not load, a test that did not finish, a tool or package missing, a planned test that has no boot-check test yet) are in common failures.
rp1-pio¶
Board |
Variants |
What it checks |
What the check runs |
|---|---|---|---|
Sqrl Acorn |
every |
the Pi 5’s RP1 PIO, which JTAG uses, is there and can be opened |
on a Pi 5 / CM5: the RP1 PIO that openFPGALoader’s rp1pio cable uses, /dev/pio0 there and openable ( |
When it fails:
It says |
Meaning, and what to do |
|---|---|
|
the Pi’s RP1 PIO, which openFPGALoader’s |
The messages any check can give (a design that would not load, a test that did not finish, a tool or package missing, a planned test that has no boot-check test yet) are in common failures.
jtag¶
Board |
Variants |
What it checks |
What the check runs |
|---|---|---|---|
Sqrl Acorn |
every |
over the P1 cable, the JTAG IDCODE and device DNA read, and the DNA is BAR0’s |
IDCODE and device DNA over P1 ( |
Digilent Arty A7 |
|
over its FT2232H, the JTAG IDCODE is an XC7A35T’s and the device DNA reads |
reads the JTAG IDCODE and device DNA; loads nothing |
Kosagi NeTV2 |
|
over the Pi’s header, the JTAG IDCODE is the variant’s part and the device DNA reads |
reads the JTAG IDCODE and device DNA; loads nothing |
Not for:
Fomu EVT (
evt): the iCE40UP5K has no JTAG port: the Fomu is loaded over USB DFU, by fobootTT FPGA Demo Board (
tt-fpga): the iCE40UP5K has no JTAG port: it is loaded through the demo board’s RP2350TT FPGA Demo Board (
tt-asic): a Tiny Tapeout chip is an ASIC, not an FPGA: nothing on it is configured over JTAGTT FPGA Demo Board (not yet known): neither a TT FPGA breakout (an iCE40UP5K, loaded through the RP2350) nor a Tiny Tapeout chip has a JTAG port
When it fails:
It says |
Meaning, and what to do |
|---|---|
|
the JTAG IDCODE is not the variant’s part: the wrong board, or the wrong |
|
the P1 JTAG chain does not hold exactly one FPGA of the Acorn’s part (the variant’s, or any Acorn’s when the variant is not known); the reason names what answered. Another part: most likely the P1 cable reaches another board’s JTAG, or the card is not the variant its PCIe IDs say. More than one device: something else is wired into the chain |
|
more than the board’s FPGA answers on its JTAG chain (an Arty or a NeTV2): another device wired into it, or a fault on the cable |
|
an Acorn’s JTAG or P2 UART cable is off or miswired |
|
an Acorn’s JTAG pin is in use by another driver, so the JTAG tool was not started. On a Compute Blade with a CM5 (kernel 6.18), TMS and the serial port’s TX are both GPIO14, and with the serial port on the kernel does not lend the pin: JTAG cannot be tested there while the serial port is on. With the header’s serial port off at boot the pin is free: How to make a Compute Blade boot ready for JTAG |
|
openFPGALoader could not have one of the JTAG pins, because a driver holds it. On a Compute Blade with a CM5 (kernel 6.18) the serial port holds GPIO14, which is also JTAG TMS: the JTAG test cannot run there while the serial port is on. With the header’s serial port off at boot the pin is free: How to make a Compute Blade boot ready for JTAG |
|
the tool’s version, not the board: openFPGALoader exited 0 but printed no |
|
the scan tool exited with an error and printed no scan: the cable or gpiochip would not open, say. The reason ends with its last line of output; more is in the report’s |
|
the IDCODE scan reported an error, even if it printed an IDCODE; its last lines are in the report’s |
|
the IDCODE scan reported an error, even if it printed an IDCODE, so the device DNA was not read over P1 JTAG; its last lines are in the report’s |
|
the DNA read over JTAG is all zeros or all ones, which is no chip’s DNA. The IDCODE read worked without TDI, so check the P1 TDI wire first. On a Raspberry Pi 5: then run |
|
an Arty’s or NeTV2’s DNA read is all zeros or all ones. Its IDCODE scan works without TDI, so check TDI first (the NeTV2’s GPIO27); then run |
|
an Arty’s or NeTV2’s DNA read failed; the reason ends with its last line. An openFPGALoader older than 0.13.0 (Debian bookworm’s) has no |
|
the P1 TDI wire does not carry, or the DNA readout is wrong. Only a good BAR0 DNA is compared: one of all zeros or all ones is pcie-bar0’s own fault ( |
The messages any check can give (a design that would not load, a test that did not finish, a tool or package missing, a planned test that has no boot-check test yet) are in common failures.
flash¶
Board |
Variants |
What it checks |
What the check runs |
|---|---|---|---|
Sqrl Acorn |
every |
both flash slots are read whole and match the release’s images |
both flash slots read whole and compared with the release’s images |
Digilent Arty A7 |
|
a test design reads the SPI flash’s JEDEC ID |
loads its test design, then runs |
Fomu EVT |
|
a test design loaded over DFU reads the SPI flash’s JEDEC ID: the EVT’s W25Q128JV (ef7018) |
loads its test design, then runs |
Kosagi NeTV2 |
|
a test design reads the SPI flash’s JEDEC ID |
loads its test design, then runs |
Not for:
TT FPGA Demo Board (
tt-fpga): the FPGA breakout has no configuration flash: the RP2350 streams each design from the PiTT FPGA Demo Board (
tt-asic): a Tiny Tapeout chip is an ASIC: it has no configuration flash to testTT FPGA Demo Board (not yet known): neither a TT FPGA breakout nor a Tiny Tapeout chip has a configuration flash
When it fails:
It says |
Meaning, and what to do |
|---|---|
|
|
|
the test design read another flash than the EVT’s W25Q128JV over the FPGA’s own SPI pins, while |
The messages any check can give (a design that would not load, a test that did not finish, a tool or package missing, a planned test that has no boot-check test yet) are in common failures.
ddr¶
Board |
Variants |
What it checks |
What the check runs |
|---|---|---|---|
Sqrl Acorn |
every |
the DRAM self-test over the whole DRAM: no errors, bandwidth at least the variant’s minimum |
the BIOS console read out (it lets the BIOS finish DRAM set-up, #47), then the DRAM BIST over the whole DRAM, two passes ( |
Digilent Arty A7 |
|
the LiteX BIOS calibrates the DDR3 and its memory test passes |
loads its test design, then runs |
Kosagi NeTV2 |
|
the LiteX BIOS calibrates the DDR3 and its memory test passes |
loads its test design, then runs |
Not for:
Fomu EVT (
evt): the Fomu EVT has no DRAMTT FPGA Demo Board (
tt-fpga,tt-asic, not yet known): the demo board has no DRAM
When it fails:
It says |
Meaning, and what to do |
|---|---|
|
the DRAM is slow or broken; |
The messages any check can give (a design that would not load, a test that did not finish, a tool or package missing, a planned test that has no boot-check test yet) are in common failures.
p2-uart¶
Board |
Variants |
What it checks |
What the check runs |
|---|---|---|---|
Sqrl Acorn |
every |
the UARTBone bridge on the P2 cable answers at both baud rates |
the UARTBone bridge on P2 at both baud rates: identifier, DNA, XADC ( |
When it fails:
It says |
Meaning, and what to do |
|---|---|
|
an Acorn’s JTAG or P2 UART cable is off or miswired |
The messages any check can give (a design that would not load, a test that did not finish, a tool or package missing, a planned test that has no boot-check test yet) are in common failures.
p2-serial¶
Board |
Variants |
What it checks |
What the check runs |
|---|---|---|---|
Sqrl Acorn |
every |
J2 and K2 on the P2 cable work in both directions through the P2 serial switch |
J2/K2 in both directions through the p2_serial switch, then the UARTBone again ( |
When it fails:
It says |
Meaning, and what to do |
|---|---|
|
a P2 serial wire is cut or miswired |
The messages any check can give (a design that would not load, a test that did not finish, a tool or package missing, a planned test that has no boot-check test yet) are in common failures.
scratch¶
Board |
Variants |
What it checks |
What the check runs |
|---|---|---|---|
Sqrl Acorn |
every |
the scratch register reads back what was written, over BAR0 and over the P2 UART |
the ctrl scratch register written and read back over BAR0 and over the P2 UART |
When it fails:
It says |
Meaning, and what to do |
|---|---|
|
the FPGA’s control scratch register did not read back what was written, or its UARTBone bridge on the P2 cable did not answer as expected. |
The messages any check can give (a design that would not load, a test that did not finish, a tool or package missing, a planned test that has no boot-check test yet) are in common failures.
p2-gpio¶
Board |
Variants |
What it checks |
What the check runs |
|---|---|---|---|
Sqrl Acorn |
every |
J5 and H5 on the P2 cable work in both directions |
J5/H5 in both directions ( |
When it fails:
It says |
Meaning, and what to do |
|---|---|
|
a P2 spare wire is cut or miswired |
The messages any check can give (a design that would not load, a test that did not finish, a tool or package missing, a planned test that has no boot-check test yet) are in common failures.
wiring¶
Board |
Variants |
What it checks |
What the check runs |
|---|---|---|---|
Sqrl Acorn |
every |
its two cables: P1 (jtag), and P2 (p2-uart, p2-serial and p2-gpio) |
|
Digilent Arty A7 |
|
each Pmod HAT wire but the six on the shared JA/JB pins carries the FPGA pin the cabling map puts there |
loads its test design, then runs |
Fomu EVT |
|
it sits on the Pi’s header: its reset, CDONE and SPI flash lines (header) and its UART lines (uart) |
|
Kosagi NeTV2 |
|
its wires to the Pi are the header’s JTAG lines (jtag) and UART lines (uart) |
|
TT FPGA Demo Board |
|
each Pmod HAT wire carries the FPGA pin the cabling map puts there (the pin-ID scan) |
loads its test design, then runs |
TT FPGA Demo Board |
|
the RP2040 drives each ui_in and uio line and the Pi reads it on its HAT pin, bit by bit |
runs |
TT FPGA Demo Board |
not yet known |
the three Pmod ribbons to the Pi’s HAT, pin by pin (how depends on the board, not yet said) |
the tests of the board’s own variant (the rows above), once the board has said which it is |
When it fails:
It says |
Meaning, and what to do |
|---|---|
|
a demo board with a Tiny Tapeout chip whose Pmod ribbon to the Pi’s Pmod HAT is not where it should be: the reason names the ribbon ( |
|
the wiring test could not make its reading (the board did not answer, its SDK could not select the factory test, too little RP2040 heap, |
|
the Pmod HAT cabling differs from the board’s expected map. The reason names, for each HAT connector, the Arty connector (or the TT’s |
The messages any check can give (a design that would not load, a test that did not finish, a tool or package missing, a planned test that has no boot-check test yet) are in common failures.
power-cycle¶
Board |
Variants |
What it checks |
What the check runs |
|---|---|---|---|
Sqrl Acorn |
every |
the FPGA restarted since the last boot’s check (scratch holds its reset value or this boot’s marker) |
the FPGA restarted since the last check ( |
When it fails:
It says |
Meaning, and what to do |
|---|---|
|
the Acorn kept its configuration across the Pi’s restart: power-cycle the Pi (PoE). The power-cycle check |
The messages any check can give (a design that would not load, a test that did not finish, a tool or package missing, a planned test that has no boot-check test yet) are in common failures.
uart¶
Board |
Variants |
What it checks |
What the check runs |
|---|---|---|---|
Digilent Arty A7 |
|
the UART test design’s BIOS banner arrives and printable text echoes back |
loads its test design, then runs |
Fomu EVT |
|
a design loaded over DFU echoes printable text back over the header’s UART |
loads its test design, then runs |
Kosagi NeTV2 |
|
printable text sent to the UART test design echoes back over the header’s UART |
loads its test design, then runs |
TT FPGA Demo Board |
|
printable text through the RP2350’s bridge to the UART test design echoes back |
loads its test design, then runs |
Not for:
Sqrl Acorn: its UART is on the P2 cable: p2-uart tests it
TT FPGA Demo Board (
tt-asic): a Tiny Tapeout chip’s projects are fixed in silicon: no UART design can be loaded; the wiring test checks its lines to the PiTT FPGA Demo Board (not yet known): only an FPGA board has a UART test, and the board did not say whether it carries an FPGA
When it fails:
Common failures lists no message of this check’s own. Under the failed test, the check’s summary shows the last lines its test printed, which say what went wrong; fpgas-<board>-debug test <check> shows all of them.
The messages any check can give (a design that would not load, a test that did not finish, a tool or package missing, a planned test that has no boot-check test yet) are in common failures.
ethernet¶
Board |
Variants |
What it checks |
What the check runs |
|---|---|---|---|
Digilent Arty A7 |
|
the design answers ARP and ping through the Pi’s USB Ethernet adapter cabled to its RJ45 |
loads its test design, then runs |
Kosagi NeTV2 |
|
the design answers ARP and ping through a Pi USB Ethernet adapter cabled to the NeTV2’s RJ45 |
not run yet (#341): until it is, the board fails its check with this test as not run |
Not for:
Sqrl Acorn: an Acorn is an M.2 PCIe card with no Ethernet
Fomu EVT (
evt): the Fomu EVT has no EthernetTT FPGA Demo Board (
tt-fpga,tt-asic, not yet known): the demo board has no Ethernet
When it fails:
Common failures lists no message of this check’s own. Under the failed test, the check’s summary shows the last lines its test printed, which say what went wrong; fpgas-<board>-debug test <check> shows all of them.
The messages any check can give (a design that would not load, a test that did not finish, a tool or package missing, a planned test that has no boot-check test yet) are in common failures.
header¶
Board |
Variants |
What it checks |
What the check runs |
|---|---|---|---|
Fomu EVT |
|
over the Pi’s header: CDONE, the iCE40 held in reset, the SPI flash’s JEDEC and unique IDs |
judges what the check read: before the tests, |
When it fails:
It says |
Meaning, and what to do |
|---|---|
|
the Fomu’s header does not reach an iCE40’s reset: it is not seated on the header, or this is not a Fomu EVT. The flash was not read |
|
the Fomu’s iCE40 runs no design (its flash’s boot image did not load), or the board was found on USB but is not on the header. Nothing on the header was driven |
|
something answered on the header’s SPI pins, but not the EVT’s flash |
The messages any check can give (a design that would not load, a test that did not finish, a tool or package missing, a planned test that has no boot-check test yet) are in common failures.
foboot¶
Board |
Variants |
What it checks |
What the check runs |
|---|---|---|---|
Fomu EVT |
|
foboot, its USB DFU bootloader, enumerates again after the reset |
judges what the check read: after that reset, the Pi’s USB is watched for foboot (1209:5bf0); nothing is loaded |
When it fails:
It says |
Meaning, and what to do |
|---|---|
|
the iCE40 booted (the |
The messages any check can give (a design that would not load, a test that did not finish, a tool or package missing, a planned test that has no boot-check test yet) are in common failures.
foboot-after¶
Board |
Variants |
What it checks |
What the check runs |
|---|---|---|---|
Fomu EVT |
|
the closing reset brings foboot back on USB, so the next user can load a design |
the last step, after every test, only when header and foboot passed: the iCE40 is reset through the header back into foboot |
When it fails:
It says |
Meaning, and what to do |
|---|---|
|
the check’s last reset, which puts foboot back for the next user, did not bring foboot back: no design can be loaded over DFU until the Fomu is power-cycled (the site operator’s power cycle of the Pi does it). With |
The messages any check can give (a design that would not load, a test that did not finish, a tool or package missing, a planned test that has no boot-check test yet) are in common failures.
sdk¶
Board |
Variants |
What it checks |
What the check runs |
|---|---|---|---|
TT FPGA Demo Board |
|
the board’s chip, shuttle, microcontroller and SDK release are a combination the SDK supports |
judges what the check read: before the tests, over the board’s USB serial: |
TT FPGA Demo Board |
not yet known |
the board’s chip, shuttle, microcontroller and SDK release are a combination the SDK supports |
the tests of the board’s own variant (the rows above), once the board has said which it is |
When it fails:
It says |
Meaning, and what to do |
|---|---|
|
the Tiny Tapeout SDK on the demo board is not a release known to work with the chip it carries. The firmware is installed by whoever looks after the board; the check writes nothing to it. The |
The messages any check can give (a design that would not load, a test that did not finish, a tool or package missing, a planned test that has no boot-check test yet) are in common failures.
dip-switches¶
Board |
Variants |
What it checks |
What the check runs |
|---|---|---|---|
TT FPGA Demo Board |
|
every DIP switch on ui_in is off |
loads its test design, then runs |
When it fails:
It says |
Meaning, and what to do |
|---|---|
|
one or more of the demo board’s DIP switches on |
The messages any check can give (a design that would not load, a test that did not finish, a tool or package missing, a planned test that has no boot-check test yet) are in common failures.
spram¶
Board |
Variants |
What it checks |
What the check runs |
|---|---|---|---|
TT FPGA Demo Board |
|
the iCE40’s 128 KB of SPRAM reads back each word’s address and its inverse, and each byte lane writes alone |
loads its test design, then runs |
When it fails:
It says |
Meaning, and what to do |
|---|---|
|
a word of the iCE40’s SPRAM did not read back what was written: the FPGA’s internal memory is faulty, or the design did not run as built. The |
|
the SPRAM test design never answered through the RP2350’s UART bridge: it did not load or did not start. The |
The messages any check can give (a design that would not load, a test that did not finish, a tool or package missing, a planned test that has no boot-check test yet) are in common failures.