The Acorn check

This page explains what the check of an Acorn is, what it does to the card, and what it can show on each carrier.

fpgas-verify is the program that checks an FPGA board from the machine it is attached to. For an Acorn its check doubles as a wiring test. Each of its tests uses a known set of wires between the card and its host. So which tests pass, and what a failing one says, point at the wire.

What the check does to the card

The check never writes the card’s flash and never loads a design into the FPGA. It drives the P1 and P2 wires, which is how it tests them, and puts the host’s pins back as it found them.

The two programs

fpgas-verify checks whichever board this host is set up for, as the check at boot does. The program fpgas-acorn-verify checks the Acorn whatever the host is set up for. On a host set up for an Acorn the two print the same.

The variants

An Acorn is sold as a CLE-215+, a CLE-215 or a CLE-101. The check’s summary names the variant it found, acorn cle-101 for example.

A card on the image it was sold with

Two tests need no design of ours in the card: pcie-link and jtag. They are the wiring tests of a card that has not been converted. The tests of the P2 wires need the fpgas.online design running in the card (How to install the fpgas.online images on an Acorn). Which test uses which wire is a table for each host. The tables: Acorn tests and their wires on a Raspberry Pi 5 and Acorn tests and their wires on a Compute Blade.

On a Compute Blade

  • Do not load a design into a card on a Compute Blade, and do not convert it. The one time a design was loaded into a card on a blade, the card’s PCIe endpoint did not come back. Neither a bus rescan nor a re-probe of the PCIe controller restored it. After the reboot that followed, the blade kept restarting for about two hours (the record of that run).

  • So the check’s result on a Compute Blade is fail, the card being on the image it was sold with. The test pcie-link passes when the card is seated, and the tests that need the fpgas.online design are not run.

  • JTAG’s TMS wire is GPIO14, which the header’s serial port also uses. In a boot with that port on (kernel 6.18), jtag fails without running the JTAG tool. In a boot with that port off, on a Compute Module 5, jtag reads the FPGA’s IDCODE and device DNA. How to make that boot: How to make a Compute Blade boot ready for JTAG.

  • The check is for a blade with a Compute Module 5. Do not run it on a blade with a Compute Module 4: what is open there is in the record.

  • The check cannot show that the two cables are right while the card is not converted. The bench check with a meter, before fitting, is what the cables rest on: How to check the cables on the bench (Compute Blade).