Acorn wiring on a Compute Blade

This page is for someone with an Acorn in a Compute Blade with a CM4 or CM5, which has no 40-pin header. It lists which wire of the card’s two connectors goes to which pin of the blade’s Extension Port and UART header. The blade’s settings are on the blade’s pins and settings.

Why JTAG and the serial pair share a line is on The line JTAG and the serial port share on a Compute Blade. An Acorn on a Raspberry Pi 5 is wired differently and has its own page. To build and fit the cables, follow The two cables on a Compute Blade.

The wiring sheet

The --pins numbers on the sheet are GPIO numbers, not printed pin numbers. Select the sheet for the full-size drawing.

Board connectors

The Acorn has two 6-pin Molex Pico-EZmate connectors. Both are on the underside of the card (the face without the FPGA and heatsink). They sit side by side along one long edge at the fan end, away from the M.2 edge connector. The silkscreen beside them reads I/O / P2 and JTAG / P1, and P2 is the one nearer the end of the card.

Pin 1 of each connector is the end nearest the M.2 edge connector, and it is GND on both. Both cables have six black wires, so a wire is told by its position from pin 1.

Each row of the table is one pin, with its signal on P2 and on P1, named after the “Pico-EZmate connectors pinout on Acorn, Nite/LiteFury” legend of the LiteX Acorn CLE-215 wiki. The legend names K2 and J2 from the host’s side. The table names them from the FPGA’s side, so K2 is the FPGA’s transmitter.

Pin	P2 (I/O)	P1 (JTAG)
1	GND	GND
2	K2 (LVCMOS33): serial TX, FPGA output	TCK: JTAG clock
3	J2 (LVCMOS33): serial RX, FPGA input	TDO: JTAG data out
4	J5 (LVCMOS33): spare GPIO	TMS: JTAG mode select
5	H5 (LVCMOS33): spare GPIO	TDI: JTAG data in
6	VCC: 3.3 V from the Acorn, cut, never connected	VCC: 3.3 V from the Acorn, cut, never connected

Warning

The VCC (3.3 V) wire of both P1 and P2 must never be connected to the host. Cut it back and insulate it. 3.3 V from the Acorn into the header can damage the Pi.

Pin numbering

Each row of the table is a header of the blade and the pin numbers it prints. This page uses the printed numbers, not Raspberry Pi header numbers. The Extension Port’s ten pins are electrically Raspberry Pi header pins 1-10, in the same arrangement. TX and RX on the UART header are named from the blade’s side. Every pin of the two headers is listed under the blade’s connectors and their GPIOs.

Header	Printed pins
Extension Port (printed “Extention Port”)	1 to 5 down the left column, 6 to 10 down the right (docs issue #130 is the picture that fixes which is which)
UART header (the vendor’s “UART Back”)	1 to 4 from the top

P1: JTAG, on the Extension Port

Each row is one wire: a P1 pin, its Extension Port pin, GPIO and direction, resistor and shared line.

P1 pin	Signal	→ Extension Port pin	Host name	GPIO	Direction	Series resistor	Same line as
1	GND	8	GND	—	—	—	—
2	TCK: JTAG clock	4	IO4	GPIO4 (GPCLK0)	Pi → FPGA	—	—
3	TDO: JTAG data out	3	IO3	GPIO3 (I2C1_SCL)	FPGA → Pi	—	—
4	TMS: JTAG mode select	9	IO14	GPIO14 (TXD0)	Pi → FPGA	—	J2 (UART 3)
5	TDI: JTAG data in	2	IO2	GPIO2 (I2C1_SDA)	Pi → FPGA	—	—
6	VCC: 3.3 V from the Acorn, cut, never connected	cut, never connected	—	—	—	—	—

P2: serial pair, on the UART header

Each row is one wire: a P2 pin, its UART pin, GPIO and direction, resistor and shared line. The 470 Ω resistor is soldered into the J2 wire near its housing end. Why it is there: The line JTAG and the serial port share on a Compute Blade. Fitting it: How to prepare the UART cable’s wires (Compute Blade).

P2 pin	Signal	→ UART pin	Host name	GPIO	Direction	Series resistor	Same line as
1	GND	2	GND	—	—	—	—
2	K2 (LVCMOS33): serial TX, FPGA output	4	RX	GPIO15 (RXD0)	FPGA → Pi	—	—
3	J2 (LVCMOS33): serial RX, FPGA input	3	TX	GPIO14 (TXD0)	Pi → FPGA	470 Ω	TMS (Extension Port 9)
4	J5 (LVCMOS33): spare GPIO	not connected: cut back and insulate	—	—	—	—	—
5	H5 (LVCMOS33): spare GPIO	not connected: cut back and insulate	—	—	—	—	—
6	VCC: 3.3 V from the Acorn, cut, never connected	cut, never connected	—	—	—	—	—

Housings

Each row of the table is the Dupont housing of one connector and the cavities that stay empty. No cavity holds two wires.

Connector	Housing	Covers	Cavities that stay empty
P1, on the Extension Port	2×5	the whole port	1, 5, 6, 7 and 10
P2, on the UART header	1×4	the whole header	1

Warning

Extension Port pins 6 and 7 and UART pin 1 are 5 V and sit inside a housing. Their cavities must stay empty. A housing turned round puts a wire there.

Each housing is marked at its pin 1, and the mark goes on printed pin 1.

When a wire does not answer: Acorn wiring faults on a Compute Blade.