How to load a design onto a NeTV2 from its board page¶

You have a NeTV2’s page open on welland.fpgas.online and a bitstream for it. You want the design to run. The load goes into the FPGA’s SRAM and is lost at power-off. A reset or a reboot also empties /home/pi, uploads included. A visitor never writes the board’s flash.

The Pi 5 steps are still waiting for their first run on a host: test-designs issue #246.

What you need¶

A NeTV2’s page, from the welland list: a board whose label says NeTV2.
A .bit file built for the board’s FPGA, here design.bit. The FPGA is an XC7A35T, or an XC7A100T on the large variant. On a Pi 3B+, step 2 of its part reads the IDCODE that tells them apart; the Pi 5 steps do not show it. The host’s own test bitstreams for both are in /usr/share/fpgas-online/netv2/bitstreams/.

Steps¶

Upload the file with the page’s upload button. It goes into /home/pi/Uploads/ on the host.
In the page’s terminal, find out which Pi the host is. The line names the model: a Pi 5 or a Pi 3B+.
```
$ cat /proc/device-tree/model
```
Follow the part below for your host.

On a Pi 5¶

List the board’s PCIe endpoint. A line is an endpoint to detach. With no line, go to step 3.
```
$ lspci -D -s 0001:01:00.0
```
Detach it. The same lspci command then prints nothing. If it still prints the line, stop. The host’s PCIe controller does not survive a load while the endpoint is enumerated.
```
$ echo 1 | sudo tee /sys/bus/pci/devices/0001:01:00.0/remove
$ lspci -D -s 0001:01:00.0
```
Load the design into SRAM through the RP1’s PIO peripheral. The pin order is TDI:TDO:TCK:TMS.
```
$ sudo openFPGALoader --cable rp1pio --pins 27:22:4:17 Uploads/design.bit
```

Rescan the bus to bring the endpoint back.

$ echo 1 | sudo tee /sys/bus/pci/rescan

List the host bridge’s driver.
```
$ ls /sys/bus/platform/drivers/brcm-pcie/
```
If it lists no 1000110000.pcie, the host bridge removed itself at boot, with no link. Bind it again, with no unbind first, and give the link a few seconds. If it lists 1000110000.pcie, skip the bind.
```
$ echo 1000110000.pcie | sudo tee /sys/bus/platform/drivers/brcm-pcie/bind
```

On a Pi 3B+¶

Read the two settings that make a load safe. The kernel console UART shares the FPGA’s serial TX pin.
```
$ sysctl kernel.sysrq
$ cat /proc/cmdline
```
If the command line has console=serial0, do not load on this host: choose another NeTV2 from the list. If sysctl does not print kernel.sysrq = 0, set it to 0.
```
$ sudo sysctl -w kernel.sysrq=0
```

See the FPGA answer on JTAG.

$ sudo openFPGALoader --cable libgpiod --pins 27:22:4:17 --detect

Load the design into SRAM. The effective JTAG clock is about 5 MHz, so a load is slow. The pin order is TDI:TDO:TCK:TMS.
```
$ sudo openFPGALoader --cable libgpiod --pins 27:22:4:17 Uploads/design.bit
```

Check¶

The load’s last line ends with done 1. With done 0 the FPGA is not configured, whatever the exit status; the STAT register printed under it says why.

On a Pi 5, after the rescan, a design with a PCIe endpoint shows the NeTV2 as a Xilinx device, and the link reads Speed 5GT/s, Width x1.

$ lspci -D -s 0001:01:00.0
$ sudo lspci -vv -s 0001:01:00.0 | grep LnkSta

On a Pi 3B+, the detect step lists an XC7A35T board as idcode 0x0362d093 with IR length 6.

What the design does shows only where the host has a USB HDMI grabber. The page’s camera then shows the board’s HDMI output, not the board. Which hosts have one is not settled (docs issue #189).

If it fails¶

What you see	Likely cause	Fix
The host crashes or drops off during the load on a Pi 5	the endpoint was still enumerated	wait for the host to come back (press Reset, as on How to reset a board, if it does not), then follow the steps again from step 1. If the host rebooted or you pressed Reset, `Uploads` is empty: upload the file again
openFPGALoader does not know the `rp1pio` cable	the host’s openFPGALoader build lacks it; only the `openfpgaloader-fpgasonline-git` package has the cable	choose another NeTV2 from the list: this host cannot load over `rp1pio`
The Pi 3B+ drops off when the design starts	the design drives the serial TX line while the kernel console and SysRq are on	make both checks of step 1 before loading again
`done 0`	the FPGA did not configure	read the STAT register printed under it, and check that the file was built for the board’s FPGA

More causes are on How to load a design into a NeTV2 on a Raspberry Pi 5 and on a Raspberry Pi 3B+.